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Frequently asked questions

LPC900 Family General FAQ

Q Do you have sample code for the LPC900 microcontrollers?
A CodeArchitect can be used to generate sample code for all the different peripherals on the LPC900 and LPC700 microcontrollers.
Q The RC oscillator is outside of the ±2.5% specification. What can cause this?
A Noise on the supply voltage VDD can interfere with the RC oscillator accuracy. Make sure the supply voltage to the LPC900 microcontroller is sufficiently decoupled.
Q Are all LPC900 IO pins 5-volt tolerant?
A All port pins are 5-volt tolerant with the exception of P3.0, P3.1, and P1.5.
Q My code executes fine on the emulator but does not run on the microcontroller. What can cause this?
A
There are a few common pitfalls:
  1. Security — When emulating, the security bits are not set, but when the microcontroller is programmed, the security bits are set. Setting the MOVCDIS security bits will inhibit any MOVC instruction from reading code memory. Look up tables are accessed by the by MOVC instructions. Try to locate look up tables in a specific sector and do not use the MOVC protection on that sector.
  2. Static vs. Code — Using the prefix static in the μVision compiler does not mean the variables will be stored in code space, the prefix code will. Make sure fixed variables are loaded into code space if they are intended to be in code space.
Q ISP programming does not work. What can cause this?
A
There are a few common pitfalls:
  1. The application board has a large capacitor between VDD and VSS. The ISP requires to switch VDD and reset. A large capacitor between VDD and VSS can cause the supply voltage to the microcontroller not to drop to 0V before it is switched on again by the ISP programming software.
  2. The microcontroller is powered through a port pin. While VDD is being switched, there is still a voltage on one of the IO pins. This will cause the microcontroller to be powered through a port pin.
  3. The UCFG1 is programmed to use an external clock source while no external clock source is provided.
Q What is the difference between ISP and ICP?
A ISP (In System Programming) requires a bootloader to run on the microcontroller and takes up 512 bytes of code space in the upper half of the top sector. ICP (In Circuit Programming) is a hardware state machine in the microcontroller accessed by a serial shift protocol. ICP allows you to use the upper half of the top sector that is otherwise used by ISP.
Q What is the difference between IAP and IAP Lite?
A The difference between IAP and IAP Lite is that IAP provides functions to do the flash operations and IAP Lite has direct access to the flash control registers. The user will have to write their own functions to change flash contents with IAP Lite.
Q What is the flash programming time for the LPC900 microcontrollers?
A The flash programming time for a single byte or a page is 4ms.
Q What is the flash erase time for the LPC900 microcontrollers?
A The flash erase time is 2ms for a single byte, a page, a sector, or the full flash memory.
Q What is the flash endurance?
A >100,000 typical erase/program cycles for each byte with a 10-year minimum data retention.
Q What is the address for the User Configuration Byte 1 (UCFG1)?
A The UCFG1 does not have a physical address-like code space. It is accessed by a separate configuration programming method.
Q When I try to debug the LPC952, my JTAG debugger will not connect to the LPC952. What is wrong?
A The reset pin must be enabled on the LPC952 for the JTAG debugging to work.
Q Can I use the edge-triggered external interrupt to wake up from power-down mode?
A The edge-triggered external interrupt requires a clock to operate properly. In power-down mode, there is no clock running. Edge-triggered interrupts might cause unexpected behavior in power-down mode.
Q Can I use the same firmware when migrating from the LPC932 to the LPC932A1?
A The LPC932A1 has the same pin-out as the LPC932, and all application code should run exactly the same. There should only be a functional difference if IAP is used in the application to reprogram the flash. When using IAP, the IAP entry point is different—0x1F on the LPC932 versus 0x1E on the LPC932A1. Also, some IAP calls require an additional security key.
Q Where can I find the instruction set for the LPC900?
A Please see our 80C51 Family Instruction Set web page.
Q What are extended SFRs or XSFRs on the LPC900 microcontrollers?
A Extended SFRs are SFRs that are located outside the regular SFR space in extended memory in the same space as XRAM.
Q What does the LPC900 memory map look like with the extended SFR space?
A
Below is the memory map of an LPC938 showing SFR and XSFR space:
Q How do I access extended SFRs in the Keil C compiler?
A
The XSFRs can be accessed like any other SFR in C. The addresses of the extended SFRs are defined in the header file. For example, an ADC result register on the LPC938 is char xdata AD0DAT0R _at_ 0xFFFE; When accessing the XSFR, the compiler will translate it into a MOVX command. Below is an example reading from AD0DAT0R:
Q When trying to enter ISP mode on the LPC900 microcontrollers, it does not work. What could be wrong?
A
The flow chart below shows the ISP entry:
Make sure the correct signals are on the VDD and reset line if the 3-pulse ISP entry method is used. The diagram below shows the 3 pulses on reset.
A A voltage on an IO pin can source current into the microcontroller when VDD is not supplied. This can cause the microcontroller not to get a good power-on reset signal. If this is the case, then ISP may not be entered by the 3 pulses on reset. Make sure that when the device is powered down, no IO pin has a voltage on it.

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