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Frequently asked questions

LPC3000 Family LPC32x0 Series FAQ

Q Is there benchmark data available for the LPC3180/LPC3250 VFP?
A
Yes. NXP Semiconductors has benchmarked the LPC3180/LPC3250 VFP performance. We used Autobench and Energybench from EEMBC. Please see the report below:
Q For the LPC3250 power supply circuitry, what is the minimum configuration (and least expensive) that you need to run an application? How many different power supplies do you need?
A
It is possible to design an LPC3250-based board with as few as two power supply voltages:
  • One 1.2 volt supply for the LPC3250 core power domains
  • One 3.3 volt supply for the IO power domains
This would not be the most power efficient design, but with only two power supplies, it would reduce the number of items on the bill of materials. The voltage supplies are used as follows:
  • 1.2V: VDD_RTC, VDD_CORE, VDD_COREFXD, VDD_PLL397, VDD_PLLHCLK, VDD_PLLUSB, VDD_FUSE, VDD_RTCCORE, and VDD_RTCOSC,
  • 3.3V: VDD_AD, VDD_IOD, VDD_EMC, VDD_IOC, VDD_IOA, and VDD_IOB
Q Do I need an external USB OTG transceiver even if I don't use OTG feature but require the USB Host or USB Device only?
A Yes. On the LPC325x, the USB pads are not differential drivers. A USB ATX tranceiver is required. NXP's ISP1301 is a popular choice among the available USB ATX tranceivers to support all three USB configuration: OTG, Host, or Device.
Q My LPC3250 Phytec board was booting the S1L as normal. I have evaluated some third party toolchains (IAR and Keil) and loaded some projects. Now, the S1L does not work?
A
If the NOR flash contents are valid, the LPC3250 bootloader ROM will execute that NOR code before it will attempt to access the NAND code. To fix this, erase the first word (address 0xe000.0000 ) on the NOR flash (with the Keil tools), reset the board, and the S1L should then boot. Please refer to Chapter 35 of the LPC3250 user manual for more details.
Q I am using the LPC3250 Phytec board and set the timeout to 0 by mistake, now I am locked out. How do I reset the timeout interval?
A On the LPC3250 Phytec board, by holding BTN1 down during reset, the default S1L loader values are reprogrammed to EEPROM. The S1L will boot again as normal.
Q What software drivers are available for the LPC3250?
A
NXP has developed a full set of drivers which support all the major peripherals and features of each MCU. We publicly release these on our website.
The Common Driver Library (CDL) has a consistent driver structure and usage across all NXP ARM microcontrollers. The CDL is high-quality code. It is consistent and follows a coding and structure standard and is well documented with comprehensive documentation for headers, APIs, and structure. It is fully tested and reviewed prior to release. At this time, the CDL supports the following compilers and others can be easily added.
  • Keil uVision
  • IAR EWARM
  • GNU
  • RVDS
With the CDL, building an application can be achieved via an IDE or command line.
Q I have heard that the LPC325x series and the LPC3180/01 do not support BSDL. Is that true?
A Both the LPC325x series and the LPC3180/01 support BSDL. Only the LPC3180 does not.
Q What is the maximum speed of PERIPH_CLK?
A We recommend using a 13MHz PERIPH_CLK, but it will operate up to 20MHz.
Q What I2C ID does the LPC3250 bootlaoder use when configuring the USB ATX?
A The bootloader supports a mode that allows booting via the USB in UART Mode. After power on, the bootloader will attempt to configure the USB PHY chip, i.e., the ISP1301. In order for the bootloader to work with the USB UART mode, the USB ATX (ISP1301) needs to have address 0x2c.
Q How do I update/program the NAND flash on the LPC3250 Phytec board??
A
NXP Semiconductors provides a flashloader utility for programming the LPC3250 Phytec board. Please contact NXP support for assistance.
Q What RTOSes have been ported to the LPC3250?
A
The following OSes have been ported to the device:
Q Is it possible to connect SDIO devices to the LPC3250?
A The LPC3250 does not support SDIO in hardware, however, there is a small system workaround that can allow SDIO support in systems using the LPC3250. An additional GPIO is needed for SDIO support from the multiplexed D2/INT signal from SDIO cards. This should provide SDIO support for network cards in the SD slot, although it hasn't been tested. This system modification was added to the LPC3250 Phytec board but is currently unsupported in the WinCE SD driver.
Q Is there a way to keep critical code always in cache?
A
Yes. The ARM926 has a 4-way, set-associative cache that permits locking of code in cache. Please refer to the ARM 926EJ-S TRM:
See Chapter 4 for information on locking code in the instruction cache.

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