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Frequently asked questions
LPC2000 Family Peripherals, System Control Block FAQ
- If you remove the clock from the LPC2000, does the PLL keep running?
- What is the oscillator start-up time and PLL lock-in time?
- How do I select the PLL as the clock source?
- Can I run the peripherals at full speed?
- What are the power and ground reference pins for the PLL?
- What is the glitch filter specification for external interrupts on the LPC2000?
- How many pins can be used as external interrupts?
- Would the PLL be active once the chip comes out of power down mode?
| Q | If you remove the clock from the LPC2000, does the PLL keep running? |
| A | Removing the clock will cause the PLL to stop working because it's an analog PLL with a phase detector. Some digital PLLs will indeed continue to work if the clock is removed. |
| Q | What is the oscillator start-up time and PLL lock-in time? |
| A | The oscillator start up time for a crystal in the range of 10 to 25MHz is typically between 0.4 and 1.95ms. This range also takes into consideration the capacitors used in the cyrstal circuit. The PLL lock-in time is 100μs. |
| Q | How do I select the PLL as the clock source? |
| A |
Application note AN10331 provides step-by-step instructions on setting up the PLL.
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| Q | Can I run the peripherals at full speed? |
| A | Yes. The peripherals clock (PCLK) can be fed by the system clock (CCLK) by setting the VPBDIV (or APBDIV) register to 1. All the peripherals can run at full speed as per the specification. |
| Q | What are the power and ground reference pins for the PLL? |
| A | Vdda and Vssa. |
| Q | What is the glitch filter specification for external interrupts on the LPC2000? |
| A | A 4ns pulse will be blocked, and a 10ns pulse will pass through. |
| Q | How many pins can be used as external interrupts? |
| A | In some devices (like the LPC23xx and LPC24xx series), all pins on ports 0 and 2 plus EXTINTx pins can be used for external interrupts. However, in other devices, only dedicated EXTINTx pins could be used as external interrupts. Please note that only the dedicated EXTINTx pins can wake the chip from power down mode. |
| Q | Would the PLL be active once the chip comes out of power down mode? |
| A | No. The PLL will be deactivated when the chip enters power down mode. The application would have to re-enable the PLL after coming out of power down. |
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