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Frequently asked questions

LPC2000 Family Peripherals, Serial Interfaces FAQ

Q What is the maximum UART speed on the LPC210x4/5/6 devices?
A The UART baud-rate is calculated as PCLK/(16 * divisor). The divisor is 16 bits long, so the maximum is when the divisor is 1. PCLK = CCLK/4, by default, in order to save power not because the UART clock has to be limited. If the maximum clock of the microcontroller is 60MHz and PCLK is set to CCLK, then the maximum UART speed (PCLK/16) is 60MHz/16 = 3.75Mbit/sec.
Q What is the maximum SPI speed on the LPC2104/5/6 devices?
A
The peripheral bus (VPB) is capable of running at the same speed as the ARM7 system bus (AHB) which is 60MHz (using VPBDIV=1). Per the user manual chapter 10, ISP features, the maximum SPI data bit rate is one eighth of the input clock rate.
The SPI rate is the peripheral clock (PCLK) rate divided by the SPI Clock Counter Register (SPCCR) value. The value of the SPCCR must always be greater than or equal to 8. PCLK is equal to the system clock, CCLK, divided by the VPB Divider Rate (VPBDIV) register contents.
If the maximum clock of the microcontroller, CCLK, is 60MHz and the VPB Divider Rate is 1, then the peripheral clock, PCLK, will also be 60MHz. If the SPI Clock Counter Register is 8, then the maximum SPI rate will be 7.5MHz (60MHz/8).
Q I am using the SPI in only the master mode. Hence, I mapped MOSI and SCLK to the respective port pins. Why don't I see any output?
A This only occurs with our LPC2104/2105/2106, LPC2114/2124, LPC2214/2224, LPC2119/2129/2292/2294/2194, and LPC2210/2290 microcontrollers. When you are using the SPI in master mode with these devices, you also need to map SSEL pin to P0.7 and drive it high. You do not need to map the MISO pin.
Q Is there a correlation of the VPB clock with the USB?
A Yes. The VPB clock should be a minimum of 18MHz while using the USB.
Q How different is the SSP port from the SPI port?
A They both have the same pin interfaceh, however, the SSP is much faster than the SPI. The SSP can operate at 30MHz in Master mode whereas the SPI can operate at around 9MHz in Master mode (considering 72MHz maximum speed operation). The SSP has a much bigger buffer than the SPI. The SSP also has an 8-frame transmit and receive FIFO wherein each frame size can vary from 4 to 16 bits.
Q Are I2C pins true open-drain pins?
A Yes. The I2C pins are true open-drain pins (as specified in the datasheet). Hence, if the LPC device is powered off, the I2C bus won't be affected.
Q Is the LPC214x series USB certified?
A Yes. The LPC214x series is USB certified. A listing of this series can be found at www.usb.org.
Q In the LPC214x series, when I enter power down mode, I don't see the current consumption dropping. What's happening?
A
The USB block has to be suspended before entering power down mode. Application note AN10493 shows the configuration for the USB block before entering power down mode.
Q Is any firmware available for the USB2.0 Device Controller?
A
Keil and IAR provide class drivers and firmware support for the USB2.0 Device Controller (for certain devices in the LPC2000 family) as part their evaluation software package.
Micrium also provides some USB ports.
Q Is there a TCP/IP stack supported for the LPC23xx and LPC24xx series microcontrollers?
A
Interniche provides a free TCP/IP stack for the LPC23xx and LPC24xx series microcontrollers.
Q SPI interrupts stop firing after a while. What could be the reason for this behavior?
A
Clearing the SPI interrupt (SPIF source in this case) is a 3-step process:
  1. Read the SPIF bit in the SPI status register.
  2. Read the SPI Data register.
  3. Finally, clear the SPIF bit in the SPI interrupt register.
After step 2, the SPIF bit in the status register is cleared. After step 3, the SPI interrupt (which was caused by the SPIF bit) is cleared. Clearing of the SPIF bit in the last step clears the SPI interrupt but does not reset the SPIF bit in the Status register.
Consider the following scenario:
  1. Read the SPIF bit in the status register.
  2. Read the SPI Data register.
The SPIF bit is now clear. Lets assume here that extra 8 clocks were received and the SPIF bit is set again. Now, 3. Finally clear the SPIF bit in the Interrupt register. The above step would clear the current SPI interrupt. The interrupt will exit fine to the main loop but since the SPIF bit is still set in the Status register, no more interrupts will be further serviced.
So servicing the SPI interrupt in a timely manner is important for the SPI interrupts to work fine.
Q I had some previous working code for the LPC2000 CAN block, and I just migrated this code to the LPC2378, and it does not work. Any idea what might be going wrong here?
A
In earlier LPC2000 devices, there used to be only one clock going into the CAN module., This was the peripheral clock (or commonly known as "pclk"). In the newer devices (like the LPC23xx and LPC24xx series), there are two separate clocks going into the CAN module:
  1. pclk — PCLK_CANx
  2. Clock for CAN filtering — PCLK_ACF
Both these clock have to be the configured in the same way for the CAN module to function.

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