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Frequently asked questions

LPC2000 Family Memory Handling FAQ

Q Do the ARM LPC products have memory-mapped chip-select?
A The 144-pin devices have four programmable memory chip-selects.
Q What is the flash endurance?
A Program flash can typically endure 100K write cycles. It is guaranteed to 10K write cycles with greater than 10-year retention.
Q Are there any flash programming tools offered by NXP Semiconductors itself?
A
NXP Semiconductors provides an ISP (In-System Programming) utility which is available as a no cost website download.
This tool only supports LPC210x, LPC213x, LPC214x, and LPC22xx families. No new devices will be added to this tool. Currently, NXP is actively supporting Flash Magic (which is built by Embedded Systems Academy) as the tool for flash programming. Flash magic supports all the devices in the LPC2000 family except LPC288x. This can be downloaded for free from the following website:
Q Why does the device not boot from external memory on a Watchdog reset?
A
This only occurs in certain LPC2000 devices if the boot loader version is less than version 1.63. The affected devices are: LPC2114/LPC2124, LPC2119/LPC2129, LPC2194, LPC2212/LPC2214, and LPC2292/LPC2294. To resolve the issue, use our boot loader utility to update to a newer version.
Q I see flash corruption when I program the on-chip flash using IAP, but ISP is working fine. What is happening?
A The Copy RAM to Flash IAP command needs the system clock frequency as a parameter. Care must me taken with this parameter. Flash corruption might occur if this parameter is incorrect. If the PLL is used in the application, then the output of the PLL should be input as KHz.
Q Some of the IAP commands need the system clock frequency as parameter. What would this frequency be if I were using the PLL?
A Please also see the FAQ above. This parameter is a very important. If the PLL is used, the value of the parameter should be the output of the PLL in KHz. Otherwise, the crystal frequency should be input as KHz.
Q On the 144-pin devices, what is the relationship between the XCLK output clock and CCLK processor clock?
A There is an n flip-flop delay between the CCLK and XCLK. This delay can change with temperature, process change, redesign, etc. Hence, we cannot guarantee the relationship between XCLK and CCLK.
Q Which pin is used for entering ISP mode?
A In most LPC2000 devices, P0.14 is used for entering ISP mode. In the LPC23xx and LPC24xx, however, P2.10 is used to enter ISP mode.
Q Can the application invoke the on-chip bootloader in software?
A
Yes, this is possible. Application Note AN10356 shows how the bootloader can be called within the application software.
Q Does the IAP or ISP interface use any SRAM space?
A Yes. Both these interfaces use some SRAM for correct operation. Please refer to the "Flash Memory System and Programming" chapter in the respective User Manual.
Q Can interrupts be handled while doing flash erase/write operations?
A Yes. Interrupts can be serviced from SRAM during flash erase/write operations. The interrupt vectors also need to be re-mapped to the SRAM space.
Q Can the on-chip flash in the LPC2000 be programmed over USB?
A
This is possible only in the LPC2888. A software programming utility is available to do this.
No other device in the LPC2000 family supports programming over USB. Only serial programming is supported in the other devices.
Q Is LPC2000 family bootloader source code available? I would like to add it to my own protocol?
A The bootloader source code is proprietary to NXP Semiconductors and therefore is not available.
Q I am using an LPC2210. It works fine when using the JTAG debugger. I have put my program into external flash. After reset, I have no activity on the CS0 line. There appears to be no attempt to fetch anything from external memory. When controlling the system from JTAG, I have no problems. What could be causing this?
A Pins P2.26, P2.27, and P0.14 need to be configured properly. P0.14 should be high at RESET to prevent the part from going into ISP mode. P2.26 and 27 determine bus configuration and also are examined at RESET. The same recommendation can be applied to any 144-pin device.

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