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Frequently asked questions
LPC1700 Series Peripherals FAQ
System Control Block
| Q |
On the LPC17xx, how many pins can be used as external interrupts? |
| A |
All pins on ports 0 and port 2 plus EXTINTx pins can be used for external interrupts.
In addition, the ARM Cortex-M3 NMI input (Non-Maskable interrupt) has been connected as a selectable function (NMI input multiplexed with P2.10) on the LPC17xx which can be used as an interrupt as well.
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| Q |
For the LPC17xx, how many types of reset are available, and what is the best way to reset the chip in software? |
| A |
LPC17xx have four types: RESET pin, watchdog reset, Power-On reset (POR), and the BrownOut Detection (BOD) circuit.
To reset the chip in software, the watchdog reset needs to be used.
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| Q |
I am operating the on-board oscillator in the LPC17xx using slave mode. I am feeding xtal1 pin with a 20MHz clock input, 50% duty cycle square wave, and at 2.7V. The XTAL1 input is spec'ed at 1.8V. Will a 2.7V clock input damage or cause problems? If so, do we need a simple voltage divider? |
| A |
The input to the crystal uses thin oxide transistors and can only tolerate 1.95V maximum for long term-reliability.
So use either a resistor divider or, even simpler, just put a capacitor to ground.
It is recommended that the drive be capacitive coupled through a 100pF capacitor, so putting a capacitor to ground will give the attenuation required.
The attenuation is Cin/(Cin+Ctogroud).
For 2.7 volts in, 50pf gives 1.8 volts.
The slave port needs a minimum of 200mV RMS.
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GPIO
| Q |
Can the internal pull-up resistors on port pins be disabled on the LPC17xx? |
| A |
There is a register which controls the activation and deactivation of the pull-up resistors.
Software has full control over the pull-up resistors on the LPC17xx.
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| Q |
On the LPC17xx, can the pull-up/pull-down resistor or open drain mode be selected for every port regardless of the function on the pin? |
| A |
The PINMODE registers control the mode of all ports.
This includes the use of the on-chip pull-up/pull-down resistor feature and a special open drain operating mode.
The on-chip pull-up/pull-down resistor and open drain operating mode can be selected for every port pin regardless of the function on this pin with the exception of the I2C pins for the I2C0 interface and the USB pins.
The pin mode cannot be selected for pins P0.27 to P0.30.
Pins P0.27 and P0.28 are dedicated I2C open-drain pins without pull-up/down resistors, and pins P0.29 and P0.30 are USB-specific pins without configurable pull-up or pull-down resistors.
Pins P0.29 and P0.30 also must have the same direction since they operate as a unit for the USB function.
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| Q |
On the LPC17xx, what is the default reset state of GPIOs? |
| A |
All GPIOs default to inputs with active pull-up after reset with the exception of the two I2C pins (P0.27 and P0.28 are open drain for I2C0 interface) and the USB pins (P0.29 and P0.30).
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| Q |
What is the input pin capacitance of the GPIO pins on LPC17xx devices? |
| A |
The maximum input capacitance for an IO pin is 2.8pF.
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| Q |
For the LPC17xx, which pins are used for SSP0? The User Manual states that P0.15, P0.16, P0.17, P0.18 or P1.20, P1.21, P1.23, P1.24 can be mapped to SSP0. |
| A |
The same SSP0 block can mapped out either on pins P0.15, P0.16, P0.17, and P0.18 or on pins P1.20, P1.21, P1.23, and P1.24.
This option allows the user to have flexibility on the port pins, and this can be configured in the PINSEL register.
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DMA
| Q |
On the LPC17xx, in General Purpose DMA controller, can I use any section on SRAM to store data on memory? |
| A |
Yes.
The user can use any section of SRAM to store data in memory.
For example, in DMA memory-to-memory mode, the user can use 0x10004000 for Source and 0x10005000 for Destination.
(0x10004000 and 0x10005000 can be changed to other addresses in 3 SRAM regions).
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| Q |
Is it possible to use the GPDMA to do transfers from memory to IO ports? |
| A |
Yes.
GPIO registers are accessible by the GPDMA controller to allow DMA of data to or from GPIOs, synchronized to any DMA request.
Please see user manual for details.
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Serial Interfaces
| Q |
What is the maximum UART speed on the LPC17xx? |
| A |
The UART baud-rate is calculated as PCLK/(16 * divisor).
The divisor is 16 bits long, so the maximum is when the divisor is 1.
The maximum clock (CCLK) of the LPC17xx can be set to 100MHz and since the peripheral clock (PCLK) can be equal to CCLK, the maximum UART speed (PCLK/16) is 100MHz/16 = 6.25 Mbit/sec.
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| Q |
What is the maximum SPI speed on the LPC17xx? |
| A |
The maximum SPI data bit rate is one eighth of the input clock rate.
The SPI rate is the peripheral clock (PCLK) rate divided by the SPI Clock Counter Register (SPCCR) value.
The value of the SPCCR must always be greater than or equal to 8.
The maximum clock (CCLK) of the LPC17xx can be set to 100MHz and, since the peripheral clock (PCLK) can be equal to CCLK, the maximum SPI rate will be 12.5 Mbit/sec (100MHz/8).
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| Q |
What is the maximum SSP speed on the LPC17xx? |
| A |
The maximum SSP speed (in master mode) is pclk/2.
The maximum clock (CCLK) of the LPC17xx can be set to 100MHz and, since the peripheral clock (PCLK) can be equal to CCLK, the maximum SSP rate (master mode) will be 50 Mbit/sec (100MHz/2).
In Slave mode, the SSP clock rate provided by the master must not exceed 1/12 of the SSP peripheral clock (selected in peripheral clock selection register).
The content of the SSPnCPSR register is not relevant.
So, the maximum SSP speed (in slave mode) will be 8Mbit/sec.
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| Q |
UART pins can be routed to more than one GPIO pin, for example, TXD1 can be routed to P0.15 and P2.0, and RXD1 can be routed to P0.16 and P2.1. Can I configure P0.15 for TXD1 and P2.1 for RXD1? Normally, one would expect P0.16 for RXD1. Also, what if I configure both P0.16 and P2.1 for RxD1 function? |
| A |
Yes.
The user can use the combination of P0.15 as TxD1 and P2.1 as RXD1.
The user just needs to make sure the function of these device pins are configured appropriately in the PINSEL register.
For receive data function (RxD1- input), the user should configure either P0.16 or P2.1.
If the user configures both pins (P0.16 and P2.1) as RxD1, then P0.16 will be used (by design, Pn.x—port with lower number "n" will be used).
For transmit data function (TxD1 - output), the user can configure both P0.15 and P2.0 as TxD1.
Data will transmitted out on both pins.
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| Q |
On the LPC17xx, is it possible to wake-up from power-down with Ethernet MACC? |
| A |
The Ethernet block supports power management with remote wake-up over LAN.
The host system can be powered-down, even including part of the Ethernet block itself, while the Ethernet block continues to listen to packets on the LAN.
Appropriately formed packets can be received and recognized by the Ethernet block and used to trigger the host system to wake up from its power-down state.
Wake-up of the system takes effect through an interrupt.
When a wake-up event is detected, the WakeupInt bit in the IntStatus register is set.
The interrupt status will trigger an interrupt if the corresponding WakeupIntEn bit in the IntEnable register is set.
This interrupt should be used by system power management logic to wake up the system.
While in a power-down state, the packet that generates a Wake-up on LAN event is lost.
There are two ways in which Ethernet packets can trigger wake-up events: generic Wake-up on LAN and Magic Packet.
Magic Packet filtering uses an additional filter for Magic Packet detection.
In both cases, a wake-up on LAN event is only triggered if the triggering packet has a valid CRC.
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Other Questions
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