Frequently asked questions

The PX1011A/PX1012A have excellent transmitter jitter performance. Both products pass the v1.0a and v1.1 specification for jitter requirements with excellent margin using various test equipment from Tektronix, LeCroy, Agilent, and Wavecrest. If you are interested in our transmitter measurement data, please contact us.

PX1011A/PX1012A Transmitter Eye Pattern (PCI Express v1.1 Specification)

PX1011A/PX1012A Transmitter Eye Pattern (PCI Express v1.0a Specification)

NXP Semiconductors and our partners have performed extensive proprietary system tests in many PC systems. These tests resulted in no receiver errors after hours of operation. The tests translate into bit error rates of << 1x10^-12.

PC Systems Tested for Receiver Performance by NXP and Partners

• ASUS P5LD2 DELUXE i945
• ASUS P5GP
• ASUS A8NE
• DELL Dimension 4700 915G
• DELL Precision 470
• Supermicro H8DCE
• Supermicro X6DA8G

PCI Express Specifications v1.0a and v1.1 require a 0.6UI (Unit Interval) receiver jitter tolerance, but the specifications do not precisely indicate how the jitter components are composed. NXP Semiconductors performed receiver bit error rate tests using Agilent's bit error rate tester. If you are interested in our receiver performance data, please contact us.

Agilent Bit Error Rate (BER) Measurement

• Equipment: Agilent J-BERT N4903A
• Where:
  TJ = Total Jitter,
  RJ = Random Jitter,
  PJ = Periodic Jitter,
  DDJ = Data-Dependent Jitter,
  UI = Unit Interval,
  ISI = Intersymbol Interference:
• 0.60UI TJ = 0.25UI RJ + 0.25UI PJ (at 15MHz) + 0.1UI DDJ
• 0.1UI DDJ = ISI module, which simulates a 9" PCB trace which is equivalent to about 0.1UI jitter and significant amplitude degradation

The results were that the PX1011A and PX1012A achieve < 1x10^-12 BER with an 800mV differential p-p input signal, which is the minimum transmit output level allowed by PCI Express specification. The 800mV differential p-p signal was fed from the pattern generator to the BERT ISI module before feeding into the PHY receiver. Without the ISI module, the PX1011A and PX1012A can achieve < 1x10^-12 BER with a 400mV differential p-p input signal.

Theoretical maximum throughput is a function of payload size and PCI Express protocol overhead. Actual throughput measurement results also depend on many factors, including software driver efficiency, PCI Express IP core efficiency, user application design, transmitter jitter, and receiver bit error rate performance. Further reduction in throughput may be due to link-layer protocol overhead such as ACK/NAK and re-transmitted packets and Flow Control Protocol (credit reporting).

Theoretical Maximum Throughput

The line speed of one-lane PCI Express is 2.5Gb/s. Because of 8B10B encoding overhead, the maximum PXPIPE data throughput is 2.5Gb/s divided by 10 bits per byte = 250MB/s. Typically, throughput increases with payload size up to a point, because of the protocol overhead bytes. For example, for a payload of 128 bytes, the theoretical efficiency is 86% (128B payload + 12B header + 8B framing), and the maximum theoretical throughput is 216MB/s. While PCI Express specification specifies the maximum payload size up to 4KB, most systems available nowadays only implement a maximum payload size of 128B or 256B.

NXP PCI Express IP partners and customers have performed various throughput measurements using the PX1011A and PX1012A, which achieve the following excellent results: