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NXP PXPIPE PHY/MAC Interface FAQ

Q What kind of PHY/MAC interface do the PX1011A and PX1012A use?
A They use a 250MHz, 8-bit data PXPIPE PHY/MAC interface. The NXP PXPIPE interface is a superset of the Intel PIPE specification. A source synchronous clock for transmit and receive data enhances the PXPIPE interface for off-chip applications.
Q How does NXP PXPIPE differ from Intel PIPE?
A The Intel PIPE interface is primarily designed for IP-to-IP transfers on the same die and uses one clock (PCLK) for both transmit and receive data. The NXP PXPIPE is enhanced for device-to-device transfers and uses source synchronous clocks for transmit and receive data. This simplifies the synchronization of data and clock signals and creates a more robust mechanism for off-chip data transfer.
Q Is NXP PXPIPE compatible with Intel PIPE?
A No. However, creating a wrapper to make PIPE and PXPIPE compatible inside a PCI Express protocol layer IP takes about as much effort as making two implementations of PIPE interoperate.
Q What is the signaling level of PXPIPE?
A PXPIPE uses a high-speed SSTL-2 I/O interface that is supported by many FPGAs, including the Xilinx Spartan-3. All PXPIPE signals (data , clock, command, and status) are SSTL-2 class I signaling. The power supply for SSTL-2 interface is 2.5V nominal (2.3V to 2.7V).
Q Do the PX1011A and PX1012A integrate SSTL-2 termination resistors internally?
A No. The PX1011A and PX1012A do not have internal SSTL-2 termination resistors.
Q Which IP vendors support the NXP PXPIPE interface?
A
Interoperability with additional vendors is expected in the future. Please check back at this webpage for an updated list, as we achieve interoperability with other PCIe IP vendors.
Q Can a low-cost FPGA handle the 250MHz, 8-bit PXPIPE interface?
A The Xilinx Spartan-3/3E FPGA has high-speed I/O capability and supports the 8-bit, 250MHz interface. Altera Cyclone II FPGA can support 250MHz SSTL-2 interface as well. The 8-bit interface enables a smaller package, fewer pins, and less PCB routing. Using a 16-bit, 125MHz interface would introduce an extra layer of logic, which inevitably increases latency.
Q How can MAC utilize the RXCLK?
A
The PXPIPE implements all signals from PHY to the MAC as source synchronous to RXCLK. The MAC has the following choices for these:
  • Use the RXCLK to capture RXDATA and status signals and also use the RXCLK as PCLK to clock the rest of the MAC where this clock is required. Insert enough delay between the captured signals and the next stage of logic (equal to the clock tree delay of RXCLK) to meet the hold time for the next stage registers.
  • Implement a shallow FIFO where the write is clocked by RXCLK and the read is clocked by MAC's local clock.
Q How can MAC generate the TXCLK?
A
The PXPIPE requires a source synchronous clock TXCLK from the MAC for the signals generated by the MAC and input to the PHY, namely TXDATA and all command signals. To provide this, a designer has the following choices:
  • Invert and send the clock that clocks the TXDATA registers as TXCLK.
  • Use 2 registers—one positive edge and one negative edge triggered—configured as toggle flops, XOR the output of the flops, and use the reconstructed clock as TXCLK. The skew between the clock to the clock regeneration registers and the TXDATA flops must be minimal.
Q How does the PXPIPE receiver detect sequence work?
A
PIPE requires the MAC to de-assert RXDET_LOOPB as soon as the PHY signals receiver detect complete by toggling PHYSTATUS to high for one clock cycle. PXPIPE relaxes this constraint as it is not possible to meet this with source synchronous clocks. The PXPIPE looks for the falling edge of RXDET_LOOPB to end the receiver detect sequence. The PHY also keeps PHYSTATUS asserted and only de-asserts it when it samples the falling edge of RXDET_LOOPB. The MAC can use the falling edge of PHYSTATUS as an acknowledgement from the PHY as the end of receiver detect sequence. In case the MAC only expects a single cycle response on PHYSTATUS, logic must be added so that the PHYSTATUS is only valid for one cycle. This can be done by registering the PHYSTATUS and using the logic below:
PHYSTATUS_new = PHYSTATUS AND (NOT PHYSTATUS_registered)

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