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PX1011A/PX1012A Applications FAQ

Q Do the PX1011A and PX1012A support ExpressCard applications?
A
Yes. The 34mm and 54mm ExpressCard specification has stringent thermal limits and form factor requirements. Our PX1011A and PX1012A are designed to support ExpressCard applications with its low power dissipation and its small and thin package.
NXP Semiconductors and Xilinx demonstrated the world's first programmable ExpressCard during the January 2005 CES. The solution is comprised of the NXP PX1011A PCI Express PHY and PDD 2016 DVB-T module, a Xilinx Spartan-3E FPGA, and an optimized Xilinx PCI Express LogiCORE IP core.
Q Do the PX1011A and PX1012A support PCI Express cable applications?
A Yes. The special requirements of cable applications (longer round-trip delay, bigger payload, larger replay buffer, more frequent Flow Control Updates) are typically handled in the MAC layer.
Q Can the PX1011A or PX1012A be used as a PCI Express endpoint or root complex?
A Yes. Both the PX1011A and PX1012A can be used as either a PCI Express endpoint or a root complex.
Q Are the PX1011A/PX1012A suitable for ASIC prototyping?
A
Yes. In fact, there are several advantages of using PX1011A / PX1012A for ASIC prototyping:
  1. The PX1011A and PX1012A already interoperate with multiple PCI Express IP vendors and work on multiple FPGA platforms.
  2. For IP-to-IP interconnect inside an ASIC, most of the PCI Express IP cores use 8-bit data interface instead of 16-bit. The 8-bit PXPIPE interface of PX1011A and PX1012A allows ASIC developers to use exactly the same 8-bit interface for both IC design and FPGA emulation. The alternative is to use an external PHY with 16-bit data interface for FPGA emulation while keeping the final integrated ASIC design with an 8-bit data interface. This alternative solution is not desirable because it inevitably adds an extra logic layer in the IC design which adds latency and makes the emulation different from the final integrated ASIC solution.
  3. The PX1011A and PX1012A can serve as a backup solution to the integrated PHY within the ASIC, as a risk mitigation measure in complex ASIC designs.

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