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SDIO controllers
Introduction
NXP's SDIO101 is an SD/SDIO/MMC/CE-ATA host controller with a standard 16-bit asynchronous memory interface.
The device conforms to the SD Host Standard Specification Version 2.0.
The SDIO101 manages the physical layer of SD, SDIO, MMC, and CE-ATA protocols and can be used together with SD Host Standard compatible driver software to add SD/SDIO/MMC/CE-ATA host functionality to a variety of microprocessor systems.
Features
- Provides 1 SD/SDIO/MMC/CE-ATA slot, operating in 1-bit, 4-bit, and 8-bit (MMC/CE-ATA) modes
- 2.5V to 3.3V host interface
- 1.8V core supply voltage
- Separate SD supply voltage pin. SD/SDIO/MMC/CE-ATA slot is able to operate over 1.8 to 3.3V voltage range
- Compliant with SDIO card specification version 2.00
- Compliant with SD Host Controller Standard Specification version 2.0
- Compliant with SD Physical Layer Specification version 2.0
- Compliant with MMC Specification version 3.31 and 4.2
- Supports CE-ATA Digital Protocol revision 1.1
- Supports CE-ATA Digital Protocol commands (CMD60/CMD61)
- Dedicated SD Card Detection input pin (insertion/removal)
- Dedicated SD Card Write Protection input pin
- Full speed (<25MHz) and high-speed (<52MHz) SD data transmissions
- Supports interrupt and slave-DMA transfer operation
- Built-in 2KB double data buffer (with 1KB maximum block size) for efficient communication with host processor
- Supports SDIO features Multi-block, Suspend/Resume, Read Wait and Wake-up Control
- Up to 400 Mbit/s read and write data transfer rates at 50MHz using MMC 8 data lines
- Up to 208 Mbit/s read and write data transfer rates at 52MHz using SD 4 data lines
- On-board crystal oscillator and PLL
- 5 levels of power saving, including a 'Hibernate mode' where oscillator, PLL and memories are switched off, and a 'Coma mode' that internally switches off supply power to most of the chip
- Additional on-board fractional clock divider for fine-grained SD clock speed control
- Cyclic Redundancy Check (CRC) for command and data
- Programmable pull-up resistor on SD CMD and SD DATn lines
- Programmable drive strength for SDCLK output to optimize SD/SDIO/MMC/CE-ATA clock speed
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SDIO Controllers
