Advanced logic features

Signal degradation can occur on an active bus when circuit boards are plugged into or extracted from a powered-up system or when a power-up and down cycle is used during system maintenance. Signal degradation is minimized by keeping the outputs of devices in the high-impedance state where the current is very low. The advanced BiCMOS logic families employ a power-up and power-down 3-State circuit that facilitates live insertion as shown below:

During V_CC ramp-up or ramp-down, the outputs are guaranteed to remain 3-State up to 2.1V for ABT and MultiByte™ families and 1.2V for LVT(16) and ALVT families, regardless of the voltage level of the data or enable input pins. Output leakage current is limited to ±100uA depending on the product family. Refer to the I_PU/I_PD specification in the data sheet.

• Available on 3-State bus interface device types in the ABT(H)16, LVT, LVT16, and ALVT families.
• Available on all 3-State bus interface device types in the MultiByte^TM family except 2377.
• Available on the following device types in the ABT family: 125, 126, 240, 2240, 241, 2241, 244, 2244, 245, 2245, 373A, 374A, 534A, 540, 541, 543A, 544, 573A, 574A, 620, 623, 640, 646A, 648, 651, 652A, 833, 853, 2952, 2953.